Memory devices are in widespread use in a variety of processor-based systems, such as computer systems. In some cases, memory devices can be mounted on the same circuit board as a processor and a memory controller, which is generally used to couple the memory devices to the processor. However, in most cases, the memory devices are part of a memory module in which several memory devices are mounted on a common substrate, such as a printed circuit board. The memory modules are generally plugged into sockets mounted on a motherboard to establish communication with a memory controller and processor. Such memory modules are commonly used in computer systems as system memory in which the memory modules are dynamic random access memory (“DRAMs”) devices.
Although the memory devices in a memory module may be coupled directly to a memory controller, in one type of memory module, known as a “registered” memory module, the memory devices are coupled to a register that is, in turn, coupled to the memory controller. More specifically, in a registered DRAM module, the command and address lines from the memory controller are coupled to a register. The register stores memory commands and addresses coupled through the command and address lines, respectively, and then couples the commands and addresses to the memory devices. Data signals are typically coupled directly to and from the memory devices without being registered. By registering the command and address signals, they can be coupled to the memory module for a relatively short period of time since it is not necessary to wait for the memory devices to latch the command and address signals. Also, registering the command and address signals avoids excessive loading of the command and address lines because the command and address lines are coupled to only a single device, i.e., the register, rather than to multiple devices, i.e., all of the memory devices.
The manner in which each of the command and address lines are routed from the register to the memory devices can significantly affect the performance of the memory module. One coupling topology, known as a “daisy chain” topology, is shown in FIG. 1A. In a daisy chain topology, a first transmission line 10, which may be a command signal line or an address signal line, extends from a register 16 to one end of a second transmission line 20 (which is a single conductor, but functions as separate segments or transmission lines 20a–g). Respective transmission lines 30a–h are coupled to spaced apart locations of the transmission lines 20(a–g). The transmission lines 30a–h each extend to an input terminal of respective memory devices 36a–h, which, in this case are DRAM devices.
A “hybrid tree” topology shown in FIG. 1B differs from the daisy chain topology of FIG. 1A in that the first transmission line 10 is coupled to the center of the second transmission line 20a rather than to one of its ends. In alternative embodiments of a hybrid tree topology, the first transmission line 10 may be coupled to locations of the second transmission lines 20(a–d) other than either one end or the center of the second transmission line 20. Like the daisy chain topology shown in FIG. 1A, respective transmission lines 30a–h are coupled to spaced apart locations of the transmission lines 20a–d and extend to input terminals of the respective memory devices 36a–h. 
Still another hybrid tree topology shown in FIG. 1C uses two separate transmission lines 20a,b coupled to the transmission lines 30a–d, 30e–h. Transmission lines 20a and 20b are made up of transmission lines 20aa, 20ab, 20ac, 20ad, 20ba, 20bb, 20bc and 20bd respectively. The transmission lines 20a,b are, in turn, coupled to the first transmission line 10 through a third transmission line 40, which joins the first transmission line 10 at the center of the transmission line 40. Transmission line 40 is made up of transmission lines 44a and 44b. Transmission lines 44a and 44b are coupled to the transmission lines 20a,b at the ends of the transmission line 40 by respective transmission lines 44a,b. 
The daisy chain and hybrid tree topologies shown in FIGS. 1A–1C can provide adequate performance at relatively slow speeds, but they provide less than optimum performance at higher operating speeds. In particular, signals coupled through the transmission line 20 (or transmission lines 20a,b in the case of the topology shown in FIG. 1C) reflect from the junctions with the transmission lines 30a–h as well as from the junction between each of the transmission lines 30a–h and its respective memory devices 36a–h, respectively. These reflections produce destructive and constructive interference at each of the junctions between the transmission line 20 and the transmission lines 30a–h that can seriously degrade signals coupled to the memory devices 36. The hybrid tree topologies shown in FIGS. 1B and 1C place the transmission lines 30a–h closer to the ends of the transmission line 20 compared to the daisy chain topology shown in FIG. 1A. Therefore, the hybrid tree topologies tend to provide better performance than the daisy chain topology. However, the hybrid tree topologies still provide less than optimum performance. Further, the hybrid tree topology shown in FIG. 1C also produces reflections from the junctions between the transmission lines 20a,b and the transmission lines 44a,b. 
Although the signal reflection problems have been described in the context of registered memory modules, the same problem can exist in other types of memory modules. For example, in a memory hub module, signals are coupled from a memory hub in the module to each of several memory devices in the module. Also, in a buffered memory module, signals are coupled from respective buffers in the module to each of several memory devices in the module. Reflections produced in these types of memory modules can degrade performance in essentially the same manner as described above.
There is therefore a need for a connection topology for routing signals to memory devices in memory modules that can avoid signal degradation caused by reflections generated at the junctions between transmission lines and memory device terminals and between different transmission lines.